High Coverage DDR4 SDRAM Memory Design and Verification Using System Verilog and UVM
Year: 2024
Type: conference-paper
Authors: Bojanki Priyanka, B Anil Kumar, D. Suresh Kumar
Institution: GMR Institute of Technology
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4408860972