Work

Clock Domain Crossing Aware RTL Synthesis using Fusion Compiler in Commercial Display Chip Design

Year: 2024

Type: conference-paper

Source: International Symposium on Artificial Intelligence and Intelligent Manufacturing (AIIM)

DOI: 10.1109/aiim64537.2024.10934572

Authors: BolunLi, Weiding Cao, Bowei Wu

Institution: Xi’an University of Posts and Telecommunications

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4408862291

FWCI:

Cites: 11

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Related to: 10