Design of 8T SRAM Cell Using Transmission Gates
Year: 2025
Type: article
Abstract: Around 70% of the power consumed and area occupied on a silicon die is due to SRAMs, which also take up about 70% of the total die space. This design provides a lower footprint, reduced latency, less expenditure of power, and increased data stability during read operations. System on Chips (SoCs) heavily relies on SRAMs, which usually take up about 70% of the total area of the die. This leaves room for potential expansion in the future. The usage of SRAMs has resulted in higher power demand, which can be addressed to the growth in the number of transistors and the associated leakage current that comes along with these transistors in smaller technologies.
Authors: Aditya Kulkarni, Lohan M, Sunitha S V, Shashank G Kubasad, Shriparna
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: diamond
OpenAlex ID: W4408866290