Work

PhasePrint: Exposing Cloud FPGA Fingerprints by Inducing Timing Faults at Runtime

Year: 2025

Type: conference-paper

Abstract: Cloud FPGAs, with their scalable and flexible nature, are rapidly gaining traction as go-to hardware acceleration platforms for compute-intensive workloads. However, their increasing adoption introduces unique security challenges. The hardware-level access that FPGAs provide leads to many vulnerabilities, including the leakage of sensitive information through data remanence and the creation of analog-domain covert channels among users. A foundational requirement in these scenarios is the ability to target an individual FPGA; knowing this, cloud vendors prevent FPGA localization by restricting access to low-level information of the underlying hardware. Beyond aiding adversaries, FPGA localization enables defenders to strategically rotate FPGA usage, preventing prolonged exposure that can lead to confidential data leakage due to long-term data remanence.

Source: ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

DOI: 10.1145/3676641.3716012

Authors: Jubayer Mahmod, Matthew Hicks

Institution: Virginia Tech

Language: English

Topic: Security and Verification in Computing

Subfield: Artificial Intelligence

Field: Computer Science

Domain: Physical Sciences

Open Access status: hybrid

Funder: Universitas Brawijaya

Award: G3187195064