Work

Implementation of Segmented Current Steering Digital to Analog Converter Using Memory Less Pipeline Dynamic Design Technique

Year: 2025

Type: article

Abstract: In the era of 5g technology, it is needed to improve speed of the circuitry used in analog and digital hardware. Digital to analog conversion is an essential process, DAC is a vital circuitry utilized for the same in the electronic systems. Our proposed current-steering DAC (CS-DAC) offers suitability for both high speed and high-resolution requirements. This work claims memory less dynamic pipeline design technique and implementation of CS-DAC using pipeline technique. CS-DAC with and without memory-less dynamic pipeline design technique is implemented using 180nm Berkeley Short-Channel IGFET Model (BSIM) version 3.3 model file. The simulation results of CS-DAC with and without pipeline design technique also compared as well.

Source: ICTACT Journal on Microelectronics

DOI: 10.21917/ijme.2025.0332

Authors: Shyamkumar Amrutlal Pankhaniya, Jayeshkumar C. Prajapati, Anju Murlibhai Vasdewani

Language: English

Topic: Analog and Mixed-Signal Circuit Design

Subfield: Biomedical Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: diamond

OpenAlex ID: W4409117964

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