Work

Towards 6G: Configurable High-Throughput Decoder Implementation for SC-LDPC Codes

Year: 2024

Type: conference-paper

Abstract: Spatially-coupled low-density parity-check (SC-LDPC) codes are considered an important candidate for the upcoming 6G standardization, owing to their superior error-correction capability and practical decoding complexity. However, current high-throughput SC-LDPC decoders rely on unrolled architectures tailored to a certain code and thus lack the necessary rate compatibility for wireless communications. In this paper, we present a fully reconfigurable decoder architecture for SC-LDPC codes. This hardware architecture can decode virtually any SC-LDPC code that fits in the allocated memories. Based on simplified routing networks, our SC-LDPC decoder can deliver extensive code length and code rate support and achieve high throughput to satisfy the requirements of 6G.

Source: 2018 52nd Asilomar Conference on Signals, Systems, and Computers

DOI: 10.1109/ieeeconf60004.2024.10942947

Authors: Yuqing Ren, Yifei Shen, Wenqing Song, Alexios Balatsoukas-Stimming, Emmanuel Boutillon, Andreas Burg

Institutions: École Polytechnique Fédérale de Lausanne, Eindhoven University of Technology, Université de Bretagne Sud, Laboratoire des Sciences et Techniques de l’Information de la Communication et de la Connaissance

Language: English

Topic: Error Correcting Code Techniques

Subfield: Computer Networks and Communications

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: green

OpenAlex ID: W4409156497

FWCI: 1.364

Cites: 24

Cited by: 3

Related to: 10