Year: 2025
Type: article
Abstract: ABSTRACT Electrolytic Cu plating is commonly used as a filling technique for via holes in through silicon via (TSV), through glass via (TGV), and organic substrates. In order to miniaturize and increase the density of substrates, the vias are becoming smaller in diameter and have a higher aspect ratio. For vias with small diameters and high aspect ratios, voids in the electrolytic Cu plating film are issues. In this study, we developed a Cu paste that can be used as a filling material for TSV, TGV, and organic substrates without creating any voids and cracks. Non-through holes with diameters ranging between 20 and 100 μm and depths ranging between 70 and 100 μm (aspect ratios from 1 to 3.5) formed in a silicon surface layer were filled with Cu paste. TGV substrates with diameters ranging between 30 and 90 μm and thickness of 300 μm (aspect ratios from 3.3 to 10) were filled with Cu paste without voids and cracks. Multilayer substrates with the diameters of 180 and 260 μm and a thickness of 6.4 mm (aspect ratios: 25, 36) were filled with Cu paste without voids and cracks. The 2.5D chip package was prepared using a TSV filled with Cu paste as a 2.5D interposer. The 2.5D chip package was verified through reliability test [thermal cycle test (TCT), high temperature storage test (HTST), un-bias high accelerated stress test (HAST) and pressure cooker test (PCT)]. After the reliability tests, the conductive resistance of the package that adopted the Cu paste was found to be within 10% of the initial value. Moreover, we found that Cu paste can be applied to 2.5D interposer as filling material, too.
DOI: 10.37665/f3z77681
Authors: Yoshinori Ejiri, Masumi Sakamoto, Chiaki Shimizu
Institution: Resonac (Japan)
Language: English
Topic: 3D IC and TSV technologies
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: diamond
OpenAlex ID: W4409159120