Year: 2025
Type: article
Abstract: Floating-Point Multiply-Accumulate (FPMAC) units are fundamental in high-performance computing applications such as digital signal processing and machine learning. This study presents an optimized FPGA-based FPMAC, integrating Booth encoding for multiplication, Wallace tree-based partial product reduction, and a 3:1 compressor for efficient accumulation. Comparative analysis highlights significant performance improvements over conventional designs, including a 30% reduction in delay, an operational frequency of 488 MHz, and a 22% increase in throughput. Additionally, power consumption is reduced by 55%, while resource utilization is optimized. The proposed architecture, with five pipeline stages, enhances computational efficiency, making it highly suitable for real-time embedded applications requiring high-speed floating-point operations. Keywords: FPGA, FPMAC, Verilog, Booth Encoding, Wallace Tree, BDSA, Compressor, Linear Zero Prediction, Delay, Power, Precision
DOI: 10.55041/ijsrem43720
Authors: Y. Ramtrivinayak,, P. Kusuma,, Sk. Hussen Vali,, Dr. N. Sambamurthy
Language: English
Subfield: Computational Theory and Mathematics
Field: Computer Science
Domain: Physical Sciences
Open Access status: bronze
OpenAlex ID: W4409166094