Year: 2024
Type: conference-paper
Abstract: Technology mapping of the logic synthesis tool ABC transforms homogeneous Boolean circuit representations (e.g., and-inverter graphs, majority-inverter graphs etc.) into Application-Specific Integrated Circuit (ASIC) targets using a cut-based Boolean matching algorithm. This entails exposing numerous k-feasible cuts to the mapping algorithm to identify an optimal match of supergate (combination of standard cells) that minimizes the overall delay without much area overhead. However, this process incurs significant timing overhead due to the need to evaluate boolean matching across an exponentially large number of cuts. We introduce LEAP: a novel machine learning-assisted cut sampling strategy that identifies and prioritizes high-quality cuts (based on delay) while filtering out low-quality ones for each node. Our extensive experimentation demonstrates that LEAP reduces the number of cuts exposed to the mapper by over 51% compared to the tool ABC, resulting in a 2% improvement in delay without incurring any area penalty. In addition, LEAP uses 35% fewer cuts with respect to the state-of-the-art SLAP tool with superior area-delay product in most cases.
Institutions: Indian Institute of Technology Guwahati, New York University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
OpenAlex ID: W4409282463