Year: 2024
Type: conference-paper
Abstract: In this work, we present GL0AM, a novel GPU accelerated logic simulator that performs delay annotated gate-level simulation, supporting a wide range of sequential components, including SRAMs, and simulation scenarios. We propose a methodology to perform simulation in 2 phases in order to increase the parallelism exposed to the GPU, where the first phase performs 0-delay cycle simulation that records sequential gate (flops, latches, and clock-gates) waveform results, and the second phase performs re-simulation to attain the remaining combinational gate waveforms. We propose to use netlist graph partitioning to minimize synchronization overheads and increase parallelism during the 0-delay simulation phase. GL0AM achieves simulation execution time speedup of 19-537X on an NVIDIA H100 GPU when compared to a commercial simulator across a diverse set of benchmarks. GL0AM provides a 2-5X speedup, iso- GPU platform and benchmark, over a recent state-of-the-art GPU-accelerated logic simulator.1
Authors: Yanqing Zhang, Haoxing Ren, Brucek Khailany
Institution: Nvidia (United States)
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
OpenAlex ID: W4409282490