Year: 2024
Type: conference-paper
Abstract: Systolic array designs are gaining popularity due to their applications in hardware acceleration for ML computing, such as CNNs and transformers. Increasingly large ML models necessitate very high circuit energy-efficiency, which is highly correlated with minimizing placement wirelength in chip physical design. However, existing placement techniques are mostly general purpose and overlook unique properties of systolic array designs. We propose a mixed-size placement approach, called SysMix, which is tailored for systolic arrays and leverage their partial regularity in hierarchical design methodologies. Experimental results from multiple CNN designs show that SysMix achieves 53% wirelength reduction and 15X speedup compared to a commercial placer and a state-of-the-art academic placer.
Authors: Donghao Fang, Hailaing Hu, Wuxi Li, Yuan Bo, Jiang Hu
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
Awards: Collaborative Research: SHF: Medium: Revitalizing EDA from a Machine Learning Perspective, Collaborative Research: SHF: Medium: Automated energy-efficient sensor data winnowing using native analog processing, CPS: Medium: Real-Time Learning and Control of Stochastic Nanostructure Growth Processes Through in situ Dynamic Imaging
OpenAlex ID: W4409282700