Year: 2024
Type: conference-paper
Abstract: Distributing a high-frequency clock signal across multiple chiplets in 2.5D integrated systems can be a challenging task due to the large physical distances among clock sinks. While silicon photonics can alleviate this challenge, conventional clock tree synthesis (CTS) algorithms that distribute an electrical clock signal cannot usefully consider the properties of light and the features of the photonic devices. These properties include the splitting of the optical power at the merging points and the effects induced by the analog receiver. A new bounded-skew synthesis methodology, targeting 2.5D integrated systems, is proposed, where an optical CTS (OCTS) algorithm determines the appropriate clock tree topology. The algorithm has as input the number and location of the photodetectors (effectively the clock sinks) and by utilizing 1 × 2, 1 × 3, and 1 × 5 splitters, the locations (loci) of the merging points are determined, such that the clock skew and power constraints are satisfied. The algorithm is applied on three benchmarks, utilizing LiNb technology, thereby demonstrating the effectiveness and generality of the approach compared to traditional CTS algorithms. For the explored benchmarks, the optical power losses are reduced up to 10.1% while bounding the skew to less than 10% of the clock period.
Institutions: Aristotle University of Thessaloniki, Harvard University
Language: English
Subfield: Computer Networks and Communications
Field: Computer Science
Domain: Physical Sciences
Open Access status: gold
OpenAlex ID: W4409282715