AI-Driven Evaluation and Optimization of Bump Pitch Effects on Chiplet and Interposer Design Quality
Year: 2024
Type: conference-paper
Abstract: 2.5D integration is gaining popularity primarily due to its ability to facilitate intellectual property (IP) reuse. Unlike conventional 2D and 3D approaches, 2.5D integration requires a more complex design and analysis process and is highly sensitive to changes in design parameters. However, research on the sensitivity of 2.5D design parameters is notably scarce, with most studies still concentrating on 2D and 3D. In this paper, we propose an AI-driven model for predicting sensitivity and an optimization methodology for 2.5D parameters, with a particular focus on bump pitch. Our approach employs advanced machine learning models to accurately predict how variations in bump pitch impact the power, performance, and area of chiplets, as well as the footprint, signal integrity, power integrity, and thermal integrity of the interposer layout. We also utilize Bayesian optimization to identify the optimal bump pitch for specific design objectives. Experimental validation of our model demonstrates high accuracy, with average relative errors of 2.69% for interpolation and 2.7% for extrapolation. Furthermore, optimization results, tailored by adjusting weights for various potential design goals, show an average improvement of 11% in area, wire length, and signal integrity-driven optimization, and 9% in power and thermal integrity-driven optimization.
Authors: Seungmin Woo, Pruek Vanna-iampikul, Sung Kyu Lim
Institutions: Georgia Institute of Technology, Burapha University
Language: English
Topic: 3D IC and TSV technologies
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
OpenAlex ID: W4409285481