Work

Leda: Leveraging Tiling Dataflow to Accelerate SpMM on HBM-Equipped FPGAs for GNNs

Year: 2024
Type: conference-paper
Abstract: Graph neural networks (GNNs) play a pivotal role in extracting insightful representations from graph-structured data, driving advancements across diverse domains. Central to GNNs is the sparse matrix-dense matrix multiplication (SpMM) kernel. However, challenges arise in accelerating SpMM due to the high sparsity and randomly distributed non-zeros in graph matrices. Recently, the high concurrency capability of high bandwidth memory (HBM) has provided a new opportunity for SpMM acceleration. Nonetheless, accelerating SpMM on HBM FPGAs is still non-trivial due to load imbalance and the random memory access patterns.
Authors: Enxin Yi, Jiarui Bai, Yijie Nie, Dan Niu, Zhou Jin, Weifeng Liu
Language: English
Open Access status: gold
OpenAlex ID: W4409307111
FWCI: 0.935
Cites: 41
Cited by: 3
Related to: 10