Year: 2024
Type: conference-paper
Abstract: Pre-silicon power and IR-drop estimation are crucial parts of the chip design process. Vector-based and vectorless assessments are commonly employed to estimate the worst peak power and dynamic IR-drop of the design. However, with rapid growth in chip scale and complexity, the waveform-driven vector-based assessment encounters the coverage challenge due to the difficulty in generating test waveforms that encompass all potential worst-case scenarios. Additionally, Vectorless assessments consistently yield overly pessimistic estimations which may lead to significant overdesign. This paper proposes a semi-vector-based assessment flow aimed at offering a more reasonable estimation of worst-case peak power and IR-drop. In the proposed assessment, functionally independent modules are identified through the analysis of module toggle activity correlation (MTAC) on the existing waveform. By making these functionally independent modules toggle simultaneously, an augmented waveform approximating the worst peak power and dynamic IR-drop scenario is actively generated while preserving a similar MTAC to the existing waveform. By applying dynamic power and IR-drop analysis to the augmented waveform, previously unaddressed weaknesses are identified. Experimental results on an industrial design indicate that the proposed worst-case assessment result is 3× and 2.5× more accurate than the vector-based result for worst peak power and dynamic IR-drop. Similarly, it is 33× and 6× more accurate than the vectorless result.
Authors: Yihan Wen, Juan Li, Bei Yu, Xiaoyi Wang
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
Funder: Chinese University of Hong Kong
OpenAlex ID: W4409307128