Work

An Innovative Digital Pulse Width Modulator and Its Field-Programmable Gate Array Implementation

Year: 2025

Type: article

Abstract: Digital pulse-width modulation (DPWM)-based controls are characterized by a non-negligible phase delay due to analog-to-digital (ADC) conversion, sampling time, carrier shape, and algorithm computation time. These delays degrade the performance in closed-loop systems, where the bandwidth must be reduced to avoid instability issues due to the reduced closed-loop phase margin. To mitigate these delays, approaches such as utilizing low-latency ADCs or increasing the sampling frequency have been employed. However, these methods are often costly and do not address the fundamental delay issues inherent to DPWMs. In this paper, a novel zero phase-delay DPWM architecture is proposed. This enhanced architecture seamlessly integrates pulse width and frequency modulation to create a programmable derivative action, capable of effectively recovering the DPWM delay. The proposed architecture employs a reliable and straightforward organization, suitable for implementation in commercial field programmable gate array (FPGA). Furthermore, this architecture inherently generates a trigger signal that can be used in numerous power electronic applications to capture the average value in piecewise linear inductor currents. The validity of the proposed architecture is substantiated through simulations and experimental tests. The final implementation is shared in an open-source resource.

Source: Electronics

DOI: 10.3390/electronics14081522

Author: Giovanni Bonanno

Institution: University of Padua

Language: English

Topic: Multilevel Inverters and Converters

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: gold

Estimated APC paid: $2,896