Work

Synthesis of a Comparator of Two Two-bit Numbers With Three Outputs

Year: 2025

Type: conference-paper

Abstract: This article considers the process of synthesizing a comparator for comparing two two-bit numbers with three output signals indicating the relationships between the numbers (greater, less, or equal). Truth tables and logical expressions for each function are provided. The structure of the comparator circuit is described, and possible optimization paths through the minimization of logical expressions are proposed.

DOI: 10.58168/cismp2024_678-681

Authors: S. Buchnev, N. Pyshnograev

Institution: Voronezh State University of Forestry and Technologies

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: gold

OpenAlex ID: W4409425412

FWCI:

Cites: 1

Cited by:

Related to: 10