Work

A 16.8 fJ/c-s 8 b 500 MS/s Asynchronous Three-Comparator SAR ADC With Background Comparator-Swapping Offset Calibration in 28 nm CMOS LPP

Year: 2025

Type: article

Abstract: This paper presents a novel comparator-swapping background offset calibration method for SAR ADCs, addressing the limitations of previous calibration techniques. The proposed method uses three comparators to eliminate reset time and calibrates offset mismatch based on the LSB conversion, leading to rapid offset convergence and reduced dependence on input signal statistics. By alternating the roles of the comparators and eliminating the need for an additional calibration cycle, the method achieves efficient calibration without the overhead of extra reference comparators. A prototype 8-bit SAR ADC implemented in a 28 nm CMOS LPP process demonstrates the effectiveness of the proposed technique, achieving a measured SNDR of 44.3 dB and SFDR of 58.4 dB at 500 MS/s, with a power consumption of 1.13 mW. The ADC occupies only 0.0033 mm², with a Walden FoM of 16.8 fJ/conversion-step. The results show that the proposed calibration method is competitive with state-of-the-art techniques, offering a highly accurate and efficient solution for background offset mismatch calibration in SAR ADCs.

Source: IEEE Access

DOI: 10.1109/access.2025.3560321

Authors: Seunghyun Kim, Yang Azevedo Tavares, Sewon Lee, Minjae Lee

Institution: Gwangju Institute of Science and Technology

Language: English

Topic: Analog and Mixed-Signal Circuit Design

Subfield: Biomedical Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: gold

Estimated APC paid: $2,075

Funders: National Research Foundation of Korea, Ministry of Science and ICT, South Korea, Samsung