Work

Spurs in Fractional-N Frequency Synthesizers Resulting From Resolution Mismatch Between the Divider Controller and the DTC: Manifestations, Analysis, and Mitigation

Year: 2025

Type: article

Abstract: The digital-to-time converter (DTC) used in fractional-Nphase locked loops is designed to cancel the accumulated quantization error (QE) arising from the divider controller. In high-resolution synthesizers, the DTC performs an additional quantization when mapping the required high-resolution phase correction to its coarse-resolution output. This inherent hard quantization nonlinearity of the DTC, which is different from the DTC’s well-known soft integral nonlinearity, causes yet another kind of inexact cancellation of the QE and induces excess spurious tones that degrade the output phase noise and jitter. This paper reveals the root cause of the “DTC’s QE” and spectral manifestation of the DTC-quantization-induced (DQI) spurs. The waveform of the DTC’s QE is derived analytically; it shows that the DQI-spur pattern is (i) determined by the fractional frequency control word and the quantization resolution of the DTC, and (ii) is independent of the type, order, and modulus of the divider controller. In view of the fact that conventional DTC linearity enhancement techniques and stochastic divider controllers have no effect on DQI-spur mitigation, we propose a novel family of DTC-enhancement methods called input-dithered quantization (IDQ). When used in DTCs, the IDQ methods are effective in eliminating DQI spurs at source with negligible phase noise or jitter penalty.

Source: IEEE Transactions on Circuits and Systems I Regular Papers

DOI: 10.1109/tcsi.2025.3557258

Authors: Xu Wang, Michael Peter Kennedy

Institution: University College Dublin

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: hybrid

Estimated APC paid: $2,645

Funder: Research Ireland