Work

Inductive GNN-Based Methodology for Accurate and Fast Average Power Estimation of Synthesized ASIC Designs From RTL Simulation Bypassing Gate-Level Simulation

Year: 2025

Type: article

Source: IEEE Transactions on Circuits and Systems I Regular Papers

DOI: 10.1109/tcsi.2025.3555891

Authors: M. B. Rakesh, Pabitra Das, K. R. Sai Pranav, Amit Acharyya

Institution: Indian Institute of Technology Hyderabad

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

Funder: Ministry of Electronics and Information technology

OpenAlex ID: W4409427241

FWCI: 1.36

Cites: 35

Cited by: 6

Related to: 10