Area Efficient and High Speed 8x8 Vedic Multiplier Design Using Parallel Prefix Adders
Year: 2024
Type: conference-paper
Authors: Unnikrishnan M S, Supreetha B S
Institution: Manipal Academy of Higher Education
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4409475465