Low-latency Fpga-based Alarm Clock System on Basys 3 With Real-time Timekeeping and Buzzer Interface
Year: 2025
Type: article
Abstract: This paper presents the design and implementation of a real-time digital alarm clock system on the Xilinx Basys 3 FPGA using Verilog HDL.Unlike traditional microcontroller-based designs, our FPGA-based system leverages hardware-level parallelism for enhanced timekeeping accuracy and responsiveness.The design includes time counting, alarm setting via onboard switches, and real-time display through a four-digit seven-segment display.When the current time matches the preset alarm, a piezo buzzer connected via the Pmod interface is triggered.
Authors: Sudheer Reddy, Tejeswara Rao P, B. Rama Chandra, D. Kiran Kumar
Institution: R.V. College of Engineering
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
OpenAlex ID: W4409553371