Work

A Cost and Speed Co-Optimized Parallel Stochastic Multiplier for Binary Inputs Supporting Variable Bit-Widths

Year: 2025

Type: article

Source: IEEE Transactions on Circuits & Systems II Express Briefs

DOI: 10.1109/tcsii.2025.3562199

Authors: Qiang He, Yudi Zhao, Zhihuai Zhang, Gang Du, Xiaofei Nie, Ye Lu, Shisheng Xiong, Kai Zhao

Institutions: Beijing Information Science & Technology University, Fudan University, Peking University

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funders: National Natural Science Foundation of China, Beijing Municipal Education Commission

Awards: G1687393570, G4136069096, G4195860161

OpenAlex ID: W4409581243

FWCI:

Cites: 22

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Related to: 10