Work

Routability-Driven Macro Placement Engine for Modern FPGAs With Complex Cascade Shape and Region Constraints

Year: 2025

Type: article

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI: 10.1109/tcad.2025.3562952

Authors: Hao Gu, Jian Gu, Keyu Peng, Jianli Chen, Jun Yang, Ziran Zhu

Institutions: Southeast University, Fudan University, State Key Laboratory of ASIC and System

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

Funders: National Natural Science Foundation of China, National Key Research and Development Program of China

Awards: G3495785756, G5200715922

OpenAlex ID: W4409640884

FWCI: 0.924

Cites: 20

Cited by: 4

Related to: 10