Work

FPGA implementation of Hardware Accelerated 64-bit Floating Point Matrix-Multiplier for GNSS Data Processing

Year: 2025

Type: conference-paper

Source: International Conference on Intelligent Systems, Advanced Computing and Communication (ISACC)

DOI: 10.1109/isacc65211.2025.10969225

Authors: Durga Digdarsini, Hem Raj Shau, Nilay Jadav, Guru Vignesh G

Institutions: Indian Space Research Organisation, Charotar University of Science and Technology, PSG College of Technology

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4409659858

FWCI: 0.928

Cites: 5

Cited by: 1

Related to: 10