Work

FPGA Implementation of an Efficient Hybrid Multiplier: A VLSI Architecture Utilizing Hybrid Adder Technology

Year: 2024

Type: conference-paper

Source: International Conference on Emerging Trends in Engineering and Medical Sciences (ICETEMS)

DOI: 10.1109/icetems64039.2024.10965035

Authors: Bala Sindhuri Kandula, G. Challa Ram, S. Koteswari, P Srinivasulu, Thathapudi Kamala Kumari, Pampana Srinivas

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4409660254

FWCI:

Cites: 24

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Related to: 10