Work

Evaluation of Worst-Case Power-Delay Performance for a 1-Bit Full Adder

Year: 2025

Type: conference-paper

Source: IEEE International Conference on Communication Systems and Network Technologies (CSNT)

DOI: 10.1109/csnt64827.2025.10967687

Authors: Pallavi Darji, Devansh Makwana, Minjal Pandya, Arpita Patel, Purvang Dalal, Vinay Thumar

Institutions: Dharmsinh Desai University, Charotar University of Science and Technology

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4409724753

FWCI: 2.3

Cites: 15

Cited by: 1

Related to: 10