Work

Design and Implementation of Low Power Energy Efficient 14T Hybrid Full Adder for Multiplier Applications

Year: 2025

Type: conference-paper

Source: IEEE International Conference on Communication Systems and Network Technologies (CSNT)

DOI: 10.1109/csnt64827.2025.10968814

Authors: Neeraj Kumar Garg, Sandeep S. Gill, Kanika Sharma

Institution: National Institute of Technical Teachers Training and Research, Chandigarh

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4409724896

FWCI: 2.358

Cites: 18

Cited by: 1

Related to: 10