Year: 2024
Type: conference-paper
Abstract: This study utilizes the ZCU102 development board with Vitis AI and Vitis IDE to establish an efficient hardware acceleration workflow for deep learning. A hardware platform integrating DPU IP was developed to support inference tasks. Pretrained models were optimized using the Vitis AI toolchain for improved FPGA runtime efficiency. Model loading and execution were implemented in C++ with Vitis AI library functions. Performance comparisons of GPU, CPU, and ZCU102 in low-light image enhancement highlight the algorithm's potential for embedded and mobile devices, offering a new direction for this technology.
Authors: Kaiping Sun, Jianping Xing, Yu Bai, Shuzhen Huang, Siqi He, Peng Sun
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: gold
OpenAlex ID: W4409832817
