Year: 2025
Type: conference-paper
Abstract: This paper presents a framework for teaching digital logic design using a 32-bit floating-point processor, developed as part of Kartikey Sharan's master's thesis.The project leverages SystemVerilog and the IEEE 754 standard to provide hands-on experience with floating-point arithmetic, FPGA implementation, and digital system design.Integrated into advanced digital logic courses at the University of Texas at Arlington, the project offers practical exposure through FPGA platforms like ModelSim and Terasic's DE10-Lite board.Students learn digital logic principles, hardware interfacing, and real-world engineering skills through this interactive, application-driven approach.
DOI: 10.18260/1-2--55081
Authors: Bill Carroll, Kartikey Sharan
Institution: The University of Texas at Arlington
Language: English
Subfield: Architecture
Field: Engineering
Domain: Physical Sciences
SDG: Quality education
Open Access status: gold
OpenAlex ID: W4409945860