Year: 2025
Type: article
Abstract: Modern digital systems rely on DRAM as main memory and flash-based SSDs for storage, forming the backbone of today’s computing infrastructure. As demands for faster processing and larger data services increase, the memory subsystems have become denser, pushing technologies to their physical limits and increasing susceptibility to faults. To ensure data integrity, two complementary approaches are employed: replacement-based techniques, which map defective cells to redundant areas, and error-correcting code (ECC) methods, which dynamically detect and correct errors. This paper theoretically investigates the most efficient use of redundancy for DRAM reliability by categorizing detects into hard faults and soft errors. Each scenario is evaluated in terms of required redundancy and residual error rate, using finite-length channel coding capacity. We compare the ECC schemes with BCH codes, which are widely favored in on-die ECC applications due to their low latency and decoding complexity.
Source: Electronics
Authors: Hyosang Ju, Dong-Hyun Kong, Kijun Lee, Myung-Kyu Lee, Sunghye Cho, Sang-Hyo Kim
Institutions: Sungkyunkwan University, Samsung Electronics (South Korea)
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
Estimated APC paid: $2,896
OpenAlex ID: W4409947717