Year: 2025
Type: article
Abstract: In this paper, a design space exploration is performed aiming at implementing a low power and high-performance hardware architecture for the double SHA-256 accelerator with optimized message scheduler. Furthermore, this study also explores the power optimization of this architecture by enabling clock gating during logic synthesis and using High Voltage Threshold (HVT) standard cells for layout implementation. The 32nm version of the SAED process design kits (PDK) was used for the ASIC implementation of the double SHA-256 hash function. The result shows that the combination of using HVT standard cell and disabling clock gating achieved the most-balanced trade-off between performance and power consumption. The resulting design could obtain a throughput of 187.9 Gbps at the frequency of 183.5 MHz with power consumption of 131.9 mW.
Institutions: University of Technology Malaysia, University of Kuala Lumpur
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: diamond
OpenAlex ID: W4409971478