Work

Power Efficient Multiplier Design for Error Resilient Edge Applications

Year: 2025

Type: article

Source: IEEE Embedded Systems Letters

DOI: 10.1109/les.2025.3566818

Authors: Manav Rathod, Anakhi Hazarika, Ayush Agrawal, Neeraj Kumar, Arunachaleashwer S.

Institutions: Birla Institute of Technology and Science - Hyderabad Campus, Birla Institute of Technology and Science, Pilani

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4410087351

FWCI: 1.381

Cites: 13

Cited by: 6

Related to: 10