Work

Evaluation of Multi-Bit Input Logic Blocks in RTL-Designed FPGA Architecture: A Framework for FPGA and ASIC Integration

Year: 2025

Type: conference-paper

Source: International Electrical Engineering Congress (iEECON)

DOI: 10.1109/ieecon64081.2025.10987880

Authors: Tomoaki Sato, Anyu Murakami, Sorawat Chivapreecha, Phichet Moungnoul

Institutions: Hokusei Gakuen University, King Mongkut's Institute of Technology Ladkrabang

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

Funders: Synopsys, Japan Society for the Promotion of Science

Awards: Development of a High-Speed and Low-Power IPS Processor Capable of Dynamic and Automatic Generation of Decision Tree Circuits, Development of Machine learning IPS processor with ASIC-FPGA Co-design and Wave Pipelining

OpenAlex ID: W4410229463

FWCI: 4.717

Cites: 8

Cited by: 2

Related to: 10