Work

Optimize Gate-All-Around Devices Using Wide Neural Network-Enhanced Bayesian Optimization

Year: 2025

Type: article

Abstract: Device design processes based on manual design experience require numerous experiments and simulations. As transistors continue to shrink, complex physical effects, such as quantum effects intensify, making the design process increasingly costly, whether based on experiments or technology computer-assisted design (TCAD) simulations. To reduce the experimental and simulation resources consumed during the design process, we propose a device optimization framework based on neural network-enhanced Bayesian Optimization (BO). We target two Figures of Merit (FoMs) of Nanowire field-effect transistor (NWFET) devices as optimization objectives: subthreshold swing (SS) and on-state current (Ion). By improving the neural network to better fit the nonlinear mapping between the objective functions and input parameters, we effectively optimize device parameters while reducing the number of TCAD simulations. Experimental results show that compared to Bayesian optimization frameworks based on Gaussian Process (GP), Random Forest (RF) and Deep Networks for Global Optimization (DNGO), our neural network-based Bayesian optimization framework reduced the number of iterations by 19.3%, 42.7% and 60.3%, respectively.

Source: IEEE Journal of the Electron Devices Society

DOI: 10.1109/jeds.2025.3569528

Authors: Jiaye Shen, Zhiqiang Li, Zhenjie Yao

Institutions: Chinese Academy of Sciences, Institute of Microelectronics

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: gold

Estimated APC paid: $1,350