Work

Dense or Sparse? Post-Packing Interconnection Analysis in FPGAs

Year: 2025

Type: conference-paper

Abstract: Packing is a crucial step of FPGA design, directly impacting interconnect complexity, routing congestion, and overall performance. This paper presents a post-packing interconnect-aware analysis, illustrating how dense (sparse) packing changes the interconnection structure. We introduce a new metric, RDensity, to define post-packing density and investigate its influence on routability. Through a comparative study of two packing tools, we demonstrate that density directly impacts routability. Our findings provide valuable insights into how packing decisions affect FPGA efficiency and offer guidance for improving FPGA packing tools and architecture design by integrating interconnect-aware methods. The goal is to achieve efficient routing while maintaining an optimal balance between cluster density, CLB pin counts, and logical block sizes.

Source: International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)

DOI: 10.1145/3728179.3728182

Authors: Xiaoke Wang, Dirk Stroobandt

Institution: Ghent University

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: hybrid

Funder: China Scholarship Council