Work

Analysis of a novel packaging technique for natural voltage balancing of series-connected SiC-MOSFETs

Year: 2025

Type: article

Abstract: This paper analyzes a novel packaging technique to improve the voltage-sharing performances of series-connected SiC-MOSFETs. The proposed method takes advantage of the parasitic capacitance network introduced by the packaging dielectric isolation layers to reduce the voltage imbalance across the series-connected devices. Firstly, the study carried out in this work explains how the parasitic capacitance networks introduced by the classic planar packaging and the gate drive circuits cause voltage imbalances across the devices. Therefore, a new packaging concept is analyzed to compensate for the effects of the gate driver parasitic capacitances. The concept is introduced and analyzed using equivalent models and mathematical approaches. To verify the analysis, the voltage sharing between two series-connected 1.2 kV SiC-MOSFETs is tested in a pulse test setup. The experimental results confirm that the proposed voltage-balancing technique can drastically improve the voltage-sharing performance of series-connected devices.

Source: Power Electronic Devices and Components

DOI: 10.1016/j.pedc.2025.100097

Authors: Luciano F.S. Alves, Pierre Lefranc, Jean-Christophe Crebier, Pierre-Olivier Jeannin, Benoit Sarrazin

Institutions: Institut polytechnique de Grenoble, Centre National de la Recherche Scientifique, Laboratoire de Génie Électrique de Grenoble, Université Grenoble Alpes

Language: English

Topic: Silicon Carbide Semiconductor Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDGs: Affordable and clean energy, Industry, innovation and infrastructure

Open Access status: gold

Estimated APC paid: $1,500