Dynamic Clock Tree Balancing Algorithm: Achieving Enhanced Performance Efficiency in Asic Design
Year: 2025
Type: conference-paper
Abstract: The creation and application of a novel clock tree balancing method that dynamically optimizes the clock distribution network in ASIC designs is the main focus of this project's effort.Improving the timing constraints, lowering clock skew, cutting down on power usage, and raising the ASIC's overall performance are the main goals.As technology has developed, ASIC designs have gotten more intricate, incorporating billions of transistors onto a single chip.It gets harder to create an efficient and well-balanced clock distribution network as the number of gates and design size increase.On the other hand, problems like clock skew, clock jitter, and excessive power consumption can arise when this clock signal is applied to every sequential part of a big and intricate ASIC design.For ASIC designs, it entails creating and constructing a dynamic clock tree balancing algorithm.Using real-time data, the program will improve clock distribution, improving timing constraints and lowering power usage.It will be evaluated against conventional techniques, verified on actual ASIC designs, and recorded for a dissertation.The project's goal is to improve ASIC design techniques to produce chips with high performance and low power consumption.
DOI: 10.15439/2024r06
Authors: J Praveen Kumar, G. Sudhagar
Institution: Bharath University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: diamond
OpenAlex ID: W4410513334