Year: 2025
Type: article
Abstract: This paper introduces an enhanced Dual-Loop Phase-Locked Loop (DL-PLL) architecture that combines a Modified design of three Stage Current Starved Voltage-Controlled Oscillator (CSVCO) having an active oscillation range between 6 to 21GHz, with a Frequency Detector (FD) and Phase Detector (PD) loops to achieve superior frequency stability, reduced phase noise, and optimized locking behavior. The dual-loop structure consists of a fast-locking inner loop FD and a low noise outer loop PD, addressing the need for efficient frequency acquisition alongside enhanced steady-state accuracy. The modified three stage CSVCO have wide tuning range, current-starved method brings accurate control over frequency of oscillation. The inclusion of a FD loop improves the frequency comparison and eliminating dead-zone issues, along with the inclusion of a PD loop performs phase detection and reduces the phase noise and jitter in the PLL output. The simulation results shows that DL-PLL having a faster lock times, lower phase noise, and reduced power consumption. This design is suitable for high performance applications, like clock synchronization, communication systems, clock generation in digital circuits, and high-frequency signal synthesis.
Authors: VISAKH C K, Dr. A Anitha
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W4410518308