Year: 2025
Type: article
Abstract: On‐chip caches occupy a significant portion of modern processors, making them increasingly vulnerable to soft errors as technology scales. While data arrays often receive robust protection via error‐correcting codes (ECCs), metadata elements such as tag fields and status bits remain inadequately protected despite their critical role in ensuring memory integrity. This paper proposes two lightweight techniques to enhance cache metadata reliability: (1) a robust three‐bit encoding scheme for status bits that tolerates single‐bit flips without data corruption and (2) a selective tag replication scheme for dirty cache blocks, enabling reliable recovery from single‐bit errors in tag arrays. Simulation results on SPEC 2006 benchmarks show that our approach recovers 97.3% of injected soft errors in cache metadata, outperforming conventional SECDED protection (93.8%) with significantly lower overhead. The proposed design incurs only 0.50% area and 1.67% dynamic power overhead on a data L1 cache. Moreover, the proposed techniques can be extended to support common cache coherence protocols in multicore systems with minimal modification.
DOI: 10.1155/jece/5008986
Author: Abdulaziz Tabbakh
Institution: King Fahd University of Petroleum and Minerals
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
Estimated APC paid: $1,100
OpenAlex ID: W4410729657