Leveraging RISC-V for HW/SW Codesign of Flexible and Efficient TinyML SoCs
Year: 2025
Type: article
Source: IEEE Design and Test
Authors: Angelo Garofalo, Luca Benini
Institutions: University of Bologna, ETH Zurich
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: closed
Award: G2258208517
OpenAlex ID: W4410738306