Year: 2025
Type: article
Abstract: High- Performance issues with typical flip-flops include power consumption at nominal supply voltages and high, erratic performance at low voltages. This study presents conditionally-bridging flip-flops (CBFFs), which have a conditionally-activated shorting device in the sense-amplifier stage, as a solution to these problems. There are two versions a single-ended design is suggested. CBFF-S for low power and area optimization, and a different version CBFF-D targeted at high-speed applications. By activating the shorting device only when needed, CBFFs achieve fully stable operation with reduced switching power. The conditionally-bridging technique reduces parasitic capacitance, simplifies design complexity, and further reduces power. In addition, it enables complete separation of pre-charged nodes during input sampling, supporting fast and reliable operation. The latching state is designed to be jitter-free and contention-free, further reducing latency and power consumption. The CBFF-S, fabricated using a 28-nm CMOS process, shows a 56.2% power saving and a 33.6% delay reduction compared to conventional designs. The CBFF-D achieves up to a 33.8% power reduction and a 24.1% delay improvement. Both designs show an improvement of at least 27.8% in the power-delay product (PDP). Monte Carlo simulations verify that the CBFFs continue to function dependably down to 0.3 V, demonstrating their suitability for near-gate voltage (NTV) applications.
DOI: 10.46632/jeae/4/2/28
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: bronze
OpenAlex ID: W4410746437