Year: 2025
Type: conference-paper
Abstract: Convolutional Neural Networks (CNNs) have been widely employed in tasks such as image recognition and object detection. However, the use of CNNs in resource-constrained terminal devices still faces significant challenges, including high computational complexity and excessive energy consumption. Field Programmable Gate Arrays (FPGAs), with their high performance, low power consumption, and flexible configurability, have emerged as an optimal solution for implementation CNN inference accelerators. This paper presents a fixed-point quantization algorithm with adjustable precision. The algorithm optimizes the data flow within the residual network and employs a two-level cache scheme to reduce memory latency. Additionally, loop unrolling and dynamic resource allocation are utilized to improve computational efficiency and enhance hardware resource utilization. In this study, ResNet50 is used as the test model, and the accelerator is validated on the Xilinx ZU49DR platform. The experimental results demonstrate that the proposed accelerator operates at a frequency of 150 MHz, with an average throughput of 696.23 GOPS and a peak throughput of 888.46 GOPS. Its processing speed is 10.67 times faster than that of the Intel i7-12700H CPU platform and 1.26 times faster than that of the NVIDIA GeForce RTX3060 GPU platform. The power consumption is measured at 7.146 W.
Authors: Haozhen Jia, Xin Chen, Daxing Dong
Institution: Nanjing University of Aeronautics and Astronautics
Language: English
Subfield: Computer Vision and Pattern Recognition
Field: Computer Science
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W4410812535