Work

Design, Implementation and Verification of Five Stage Pipeline RISC-V Core (RV32I ISA)

Year: 2025

Type: conference-paper

Source: International Conference on Electrical, Computer and Communication Engineering

DOI: 10.1109/ecce64574.2025.11013913

Authors: Shahriar Ahmed, A. B. M. Harun-Ur-Rashid

Institution: Bangladesh University of Engineering and Technology

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4410852945

FWCI: 7.138

Cites: 18

Cited by: 8

Related to: 10