Work

Performance Optimized 32-bit Multiplier: Integrating Vedic and Karatsuba Techniques

Year: 2025

Type: conference-paper

Source: Devices for Integrated Circuit (DevIC)

DOI: 10.1109/devic63749.2025.11012447

Authors: K. V. Gowreesrinivas, B. Vennela, L. Sasank, A. Sai Raghav, D. Venkata Satyanarayana

Institution: Anil Neerukonda Institute of Technology & Sciences

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4410853772

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Cites: 11

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Related to: 10