Work

8-Bit Approximate Multiplier using Approximate Full Adder

Year: 2025

Type: conference-paper

Source: Devices for Integrated Circuit (DevIC)

DOI: 10.1109/devic63749.2025.11012648

Authors: Dhulipala Karthikeya, P. R Teja Sree, Guru Prasad Mishra

Institution: National Institute of Technology Raipur

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4410854152

FWCI: 7.075

Cites: 10

Cited by: 3

Related to: 10