Work

Numerical Simulation for Analog Performance Assessment of Vertically Stacked FeFinFET

Year: 2025

Type: conference-paper

Source: Devices for Integrated Circuit (DevIC)

DOI: 10.1109/devic63749.2025.11012622

Authors: Kajal Verma, Yash Pathak, Rishu Chaujar

Institution: Delhi Technological University

Language: English

Topic: Ferroelectric and Negative Capacitance Devices

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funder: Delhi Technological University

OpenAlex ID: W4410854265

FWCI:

Cites: 28

Cited by:

Related to: 10