Work

High Speed 16T DPTL Full Adder with Reduced Power Dissipation

Year: 2025

Type: conference-paper

Source: Devices for Integrated Circuit (DevIC)

DOI: 10.1109/devic63749.2025.11012577

Authors: Evanglin Kiruba S, Harshinipriya L B, Senthamizh Selvi R

Institution: Easwari Engineering College

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4410855138

FWCI: 2.277

Cites: 21

Cited by: 1

Related to: 10