Year: 2025
Type: article
Abstract: In this project focuses on enhancing 32-bit RV32I Version 2.0 processor robustness and real – time capabilities through the integration of advanced error handling and real-time capabilities through the integration of advanced error handling mechanisms and features tailored for Real-Time Operating System (RTOS) support. To improve reliability, a sophisticated Interrupt Error Checker (IEC) is combined with robust Error Correction Codes (ECC). The IEC classifies interrupts, performs error checks related to interrupt handling, and provides detailed error information, while ECC protects data integrity in memory and registers. This synergistic combination creates a multi-layered defense against errors, crucial for mission critical systems. Simultaneously, the design addresses RTOS requirements by focusing on deterministic execution and low-latency interrupt handling. Techniques for deterministic execution include predictable instruction timing, cache management strategies (locking, partitioning, scratchpad memory), and simplified pipeline design. Low-latency interrupts are achieved through fast dispatch, prioritized interrupts, interrupt nesting, and minimized overhead. Additional RTOS-related features, such as atomic operations and hardware task management support, are also considered. This combined approach aims to create a processor capable of reliable operation in demanding real-time environments, ensuring both integrity and timely responsiveness to critical events
Authors: K.Venkanna Niadu, Akurathi Yamini, Yalla Naga Venkata Satya Ajay Kumar, Srinivasula Subhadra Supraja, Gudiwada Sushma
Language: English
Topic: Real-Time Systems Scheduling
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: gold
OpenAlex ID: W4410861697