Work

Efficient and Scalable Place and Route Methodology for Large-Scale Hierarchical Designs: Achieving Faster Turnaround Time and Predictability

Year: 2025

Type: conference-paper

Source: International Symposium on Quality Electronic Design (ISQED)

DOI: 10.1109/isqed65160.2025.11014365

Authors: Subhadeep Aich, Rajanikant Sakariya, Vivek Joshi

Institution: Texas Instruments (India)

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4410887356

FWCI:

Cites: 5

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Related to: 10